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HV574 100 MHz, 80-Channel Serial To Parallel Converter With Push-Pull Outputs
Ordering Information
Package Options Device HV574 100 Lead Quad Plastic Gullwing HV574PG Die HV574X
Features
Processed with HVCMOS(R) technology 5V CMOS logic Output voltages up to 80V Low power level shifting 100MHz equivalent data rate using four dynamic shift registers Static latched data outputs Forward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched Hi-Rel processing available
General Description
The HV574 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for printer applications. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device has 4 parallel 20-bit dynamic shift registers, permitting data rates 4X the speed of one ( they are clocked together). There are 80 static latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT80). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE (latch enable) input is high. The data in the latches is stored when LE is low.
Absolute Maximum Ratings
Supply voltage, VDD1 Output voltage, VPP1 Logic input levels1 Ground current 2 -0.5V to +7.5V -0.5V to +90V -0.3V to VDD +0.3V 1.5A 1200mW -40 to 85C -65C to +150C 260C
Continuous total power dissipation 3 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
Notes: 1. All voltages are referenced to GND. 2. Limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to 85C at 20mW/C.
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1
HV574
Electrical Characteristics (over recommended commercial operating conditions unless noted)
DC Characteristics
Symbol IDD IPP IDDQ VOH VOL IIH IIL Parameter VDD supply current Quiescent VPP supply current Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current VPP - 9V VDD - 0.5 3.75 0.5 1.0 -1.0 Min Max 30 100 100 100 Units mA A A A V V V V A A Conditions VDD = VDD max fCLK = 25MHz Outputs high Outputs low All VIN = VDD IO= -30mA, VPP = 80V IO= -100A IO = 15mA, VDD = 5V IO= 100A VIH = VDD VIL = 0V
AC Characteristics (TA = 85C max. Logic signal inputs and Data inputs have tr, tf 5ns [10% and 90% points])
Symbol fCLK tWL,tWH tSU tH tON, tOFF tDHL tDLH tDLE* tWLE tSLE tr, tf Parameter Clock frequency Min 0.001 0.001 Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock rises Output rise/fall time 25 25 0 1.0 20 0 15 500 38 38 Max 25 20 MHz ns ns ns ns ns ns ns ns ns s CL = 600pF, HVOUT from 0 to 60V CL = 15pF CL = 15pF, VDD = 5.0V CL = 15pF, VDD = 5.0V Units Conditions VDD = 4.5V, TJ = 25C VDD = 4.5V, TJ = 125C
* tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Recommended Operating Conditions
Symbol VDD VPP VIH VIL fCLK TA Logic supply voltage Output voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Parameter Min 4.5 12 VDD -0.5V 0 0.001 -40 0.5 25 +85 Max 5.5 80 Units V V V V MHz C
Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operation.
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HV574
Input and Output Equivalent Circuits
VDD VDD VPP
Input
Data Out
HVOUT
GND Logic Inputs
GND Logic Data Output
GND High Voltage Outputs
Switching Waveforms
VIH Data Input 50% tSU Clock 50% tWL 50% tWH 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% 50% VIL VOH Data Valid VIL
Latch Enable tDLE
50% tWLE
50% tSLE
VIH VOL
HVOUT w/ S/R LOW tOFF HVOUT w/ S/R HIGH
90% 10% tf
VOH VOL
10% tr tON
90%
VOH VOL
3
HV574
Functional Block Diagram
VDD
LE
BL
POL
VPP
DIR DINA DOUTA 20-bit shift register
HVOUT1
HVOUT20
CLK HVOUT21 DINB DOUTB 20-bit shift register
HVOUT40
HVOUT41 DINC DOUTC 20-bit shift register
HVOUT60
HVOUT61 DIND DOUTD 20-bit shift register
HVOUT80
GND
4
HV574
Function Table
Inputs Function All O/P High All O/P Low O/P Normal O/P Inverted Data Falls Through (Latches Transparent) Data Stored/ Latches Loaded Data X X X X L H L H X X DINX DINX I/O Relation DOUTX DOUTX
Notes:
Outputs BL L L H H H H H H H H H H H H POL L H H L H H L L H L H H H H DIR X X X X X X X X X X H H L L L H L H * * Qn Qn +1 Qn Qn +1 Qn Qn -1 Qn Qn -1 Shift Reg HV Outputs H L No inversion Inversion L H H L Stored Data Inversion of Stored Data New H or L Previous H or L Previous H or L New H or L DOUTX DOUTX DINX DINX Data Out
CLK X X X X X X
LE X X X X H H H H L L H L L H
* = dependent on previous stage's state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift.
Pin Configuration
100-Pin PG Package Pin Function Pin 1 HVOUT30 26 2 HVOUT29 27 3 HVOUT28 28 4 HVOUT27 29 5 HVOUT26 30 6 HVOUT25 31 7 HVOUT24 32 8 HVOUT23 33 9 HVOUT22 34 10 HVOUT21 35 11 HVOUT20 36 12 HVOUT19 37 13 HVOUT18 38 14 HVOUT17 39 15 HVOUT 16 40 16 HVOUT15 41 17 HVOUT14 42 18 HVOUT13 43 19 HVOUT12 44 20 HVOUT11 45 21 HVOUT10 46 22 HVOUT9 47 23 HVOUT8 48 24 HVOUT7 49 25 HVOUT6 50 Function HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 N/C VPP HVGND DINA DINB DINC DIND VDD POL LE CLK DIR BL GND DOUTD DOUTC DOUTB DOUTA HVGND VPP Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Function HVOUT80 HVOUT79 HVOUT78 HVOUT77 HVOUT76 HVOUT75 HVOUT74 HVOUT73 HVOUT72 HVOUT71 HVOUT70 HVOUT69 HVOUT68 HVOUT67 HVOUT66 HVOUT65 HVOUT64 HVOUT63 HVOUT62 HVOUT61 HVOUT60 HVOUT59 HVOUT58 HVOUT57 HVOUT56 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function HVOUT55 HVOUT54 HVOUT53 HVout52 HVOUT51 HVOUT50 HVOUT49 HVOUT48 HVOUT47 HVOUT46 HVOUT45 HVOUT44 HVOUT43 HVOUT42 HVOUT41 HVOUT40 HVOUT39 HVOUT38 HVOUT37 HVOUT36 HVOUT35 HVOUT34 HVOUT33 HVOUT32 HVOUT31
Package Outlines
100 81
1
80
30
51
31
50
top view 100-Lead Plastic Quad Flat Package ("Gullwing" Package)
11/12/01
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com

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